1. Field of the Invention
This invention relates generally to checkpointing and restoring processor registers in systems that support speculative mechanisms, and more particularly to a system and method for implementing incremental register checkpointing for transactions and in other speculation contexts.
2. Description of the Related Art
Speculative mechanisms often require the values of a processor's registers (i.e. the processor's register file) to be saved (or “checkpointed”) so that they may subsequently be restored in the case of misspeculation. Examples of speculative mechanisms include transactional memory (TM) and thread-level speculation (TLS), as well as software-transparent speculative mechanisms. In some existing processors, such checkpointing of the register file is implemented in hardware each time a transaction or other speculative mechanism is invoked. Checkpointing registers and restoring registers when a transaction or speculative episode is aborted can be very fast (e.g., single cycle) operations, in some systems. However, existing hardware approaches to register checkpointing have a number of shortcomings that limit their utility and effectiveness in many contexts. Alternatively, the register file can be saved in memory by software and subsequently restored when necessary. This approach requires no special hardware support, but it is too slow to be suitable for general use. For example, it may be prohibitively slow for use with small transactions, for which it is critical to keep latency low.